Flash memory is a type of memory used for non-volatile computer storage. Flash memory does not require power to maintain the information stored on the chip. However, over time, a charge distribution in cells in the flash memory may change. Therefore, a reference voltage (Vref) used to correctly read a value from a location in a flash memory whose charge distribution has changed may need to be changed to avoid complications from the shifting charge distribution.
Flash memory stores information in an array of memory cells made from floating gate transistors. A single level cell (SLC) device stores one bit of information per cell while a multi-level cell (MLC) device stores more than one bit per cell. Flash memory stores data by programming the cell to different threshold voltage (Vth) values. In a one bit/cell flash (SLC), flash cells have one nominal Vth while in a two bits/cell flash, cells have four nominal Vth values. Both SLC and MLC devices may experience distribution charge shift and thus Vref adaptation may be desired for both types of devices. FIG. 1 illustrates charge distribution shifts in an SLC device. The solid lines labeled T1 illustrate the charge distribution before cycling and data retention while the dotted lines labeled T2 illustrate the charge distribution after cycling and data retention. FIG. 2 illustrates charge distribution shifts in an MLC device. Once again solid lines illustrate charge distribution before cycling and data retention and dotted lines illustrate charge distribution after cycling and data retention.
Flash memory devices may store both data and error correction data. Data retrieval is achieved by determining the threshold voltage (Vth) of the flash cell where Vref is applied. The determination whether Vth<Vref or Vth>=Vref is made by sensing the drain-to-source current. The determination whether Vth<Vref or Vth>Vref controls whether the value read is interpreted as being a one or a zero. The error correction data may take the form of an error correcting code (ECC). When data is read from a flash memory cell, a determination can be made concerning whether the data was read correctly by referencing the ECC. For example, the ECC may help determine whether a value interpreted as a one is supposed to be interpreted as a one.
Data that originally was stored properly and read correctly may, over time, be read incorrectly due, for example, to the changing charge distribution. In an SLC device, there are two types of bit errors, a zero that is incorrectly read as a one, and a one that is incorrectly read as a zero. FIG. 3 illustrates an overlap between charge distributions. The overlap is the area where bit errors may be experienced due to charge distribution shift. Region E01 represents an area where a zero may be incorrectly read as a one and region E10 represents an area where a one may be incorrectly read as a zero. The position of Vref will determine the size of regions E01 and E10, and thus will determine whether there is a higher likelihood of errors where a zero is incorrectly read as a one (E0--1) or of errors where a one is incorrectly read as a zero (E1--0).
Several conventional approaches have been employed to try to manipulate Vref in attempts to improve a bit error rate (BER) for a flash memory device. However, these approaches may have been slow, inefficient, or may have required multiple reads of a cell. One conventional approach involved doing multiple precise analog read outs using multiple fractional reference voltages in an attempt to fully understand where the charge distribution is positioned. While accurate, this approach may have yielded undesired consequences. For example, flash cells may only be able to experience a finite number of read cycles before wear begins to negatively impact the integrity of the storage. The negative impact can be, for example, the charge distribution shift. Therefore it may be unwise to force a flash location to undergo multiple read cycles while trying to figure out a Vref adaptation to account for charge distribution shift caused by wear associated with PE cycles. It may be unwise to figure out the Vref adaptation using an approach that can contribute to further charge distribution shifts.
One reliability issue with MLC flash memory devices is that the margins between different nominal Vth shrink comparing to SLC flash memory devices and therefore the tolerance to noise/disturbances reduces significantly. Therefore, Vth shift issues may be more complicated in MLC flash memory devices.